1. Field of the Invention
The present invention generally relates to characterization of lithographic exposures and, more particularly, to measurement of critical dimensions of very small lithographic exposure patterns such as features suitable for formation of semiconductor integrated circuits.
2. Description of the Prior Art
It has been recognized that formation of electrical elements (e.g. transistors, capacitors, interconnects and the like) of integrated circuits at smaller sizes and increased density provides benefits in both performance and functionality. Increased proximity of devices reduces signal propagation time and increases noise immunity while increased numbers of electrical elements on a chip of a given size allow increased circuit complexity and additional signal processing functions to be provided. Improved economy of manufacture also generally results from increased integration density since more electrical elements can be simultaneously formed by a given process.
While semiconductor device designs and the processes for their formation have become highly sophisticated in recent years and many self-aligned processes are known for forming various semiconductor structures at dimensions smaller than lithographic resolution, at least one lithographic process is required for the formation of any active or passive electrical element in order to define its location and its basic dimensions. A lithographic process includes the exposure of a resist with some form of energy (e.g. light, charged particles, x-rays, etc.) to which the resist is sensitive in a pattern which is subsequently developed to remove selected areas of the resist to allow processes to be selectively carried out where resist has been removed. Therefore, the quality of the exposure of the resist is of paramount importance to the formation of integrated circuits in accordance with a given design.
Various techniques are known and have been used to evaluate lithographic exposures and each has become substantially obsolete, in turn, as increased integration density and reduced size of electrical elements has required increased precision of measurement of critical dimensions. Further, increased complexity of integrated circuits and the number of processes required for their formation has required levels of throughput to be maintained or increased to limit manufacturing costs. Therefore there is substantial economic incentive to provide measurement of critical dimensions of lithographic exposure in reduced time.
For example, an exposure of a pattern or feature including a critical dimension of interest can be made with any exposure tool. Generally a test pattern is formed in a reticle and an image thereof projected on a resist-coated target, usually employing the tool to demagnify the image by a factor of four or five. The resist is then developed in the usual manner and the critical dimension measured.
Critical dimensions which are relatively large by current standards could be directly measured by inspection with a scanning electron microscope using the current of backscattered electrons to detect the edges of the feature including the critical dimension of interest. However, this technique requires a period of about ten seconds to measure a single dimension and precision is limited to about five nanometers.
Numerous measurements (e.g. a few dozen to several hundred sites per field over a matrix of several dozen fields on a wafer) are generally made, particularly for calibration of the tool to obtain the best imaging across the entire field as well as during manufacturing to ensure the tool performance remains within tolerances. Such numbers of measurements require substantial time, particularly when about ten seconds are required for each individual measurement with electron microscopy, as alluded to above. Further, scanning electron microscopy requires measurements to be made at high vacuum levels, requiring substantial time to achieve. Such a long measurement time adversely impacts throughput, especially in a manufacturing environment.
Additionally, precision of much less than one nanometer is required for integrated circuit designs at the current state of the art. Increase of electron beam power to reduce measurement time and/or increase precision tends to erode the pattern being measured. Other problems have also been associated with scanning electron microscope measurements. As noted in U.S. Pat. No. 6,094,256, which is fully incorporated by reference, the resolution of even state of the art scanning electron microscopes is only marginally sufficient for present integrated circuit designs and will be insufficient for foreseeable designs.
Further, the nature of electron microscopy requires bombardment of a substrate with particles and the resultant secondary emissions that are captured for imaging can contaminate devices in integrated circuits adjacent the test patterns when applied to manufacturing environments. In such environments, the wafer used for the test exposure is often discarded or the resist removed and the wafer reprocessed without measurements being concurrently made. Moreover, the cost of specialized electron microscope measurements coupled with the low throughput thereof add significantly to the cost of integrated circuit manufacture.
U.S. Pat. No. 6,094,256, however, teaches use of a measurement of a length much larger than the critical dimension in order to provide an indirect measurement of critical dimension width. As disclosed therein, partial exposures of parallel line patterns (where the critical dimension is line width) are made with the patterns displaced through a small angle between partial exposures. This technique results in an array pattern of small parallelograms or rhombus shapes being exposed and developed. The major dimension of the shape between the most widely separated points of the rhombus (hereinafter sometimes referred to as the major, longer or greater diagonal) is related to the critical dimension, CD, by the angle change between the partial exposures in accordance with the equation Lxe2x88x9dCD/sin xcex1. Since sin xcex1 is very small at small angles, xcex1, CD is effectively multiplied in the measurement of L. Thus, by choosing a suitably small angle between exposures or an appropriately tapered pattern, a length dimension much larger than the critical width dimension can be measured and a measurement of the critical dimension calculated from that length.
However, even this technique is of marginal sensitivity at very small critical dimensions even though the critical dimension may be greatly multiplied when the angle between partial exposures is small. The width of a scanned laser beam or dimensions of a pixel of a detector such as a charged coupled device (CCD) generally used for detecting the rhombus shaped test marks is necessarily finite and limits resolution of the length measurement that can be made to a similarly finite width of a laser beam in the reflected and diffracted light response peak detected by, for example, a charge coupled device (CCD) array as a laser beam pattern is scanned lengthwise over the marks. The cost of apparatus for producing a sufficiently narrow laser beam to support adequate measurement resolution is also a significant component of the overall cost of integrated circuit manufacture. Further, the information concerning critical dimensions is confined to the tips of the test marks which is a very small portion of the test marks; resulting in inefficiency relative to required chip area of the test marks.
As a practical matter, the amount of multiplication available is limited because the narrow tips of the rhombus shapes become unstable using currently available materials and processes and the measurable length may be uncontrollably foreshortened at very small angles. This effect compromises both the accuracy, precision and repeatability of measurements made. That is, the effects of any such instability is relatively large in comparison with the portion of the test marks which carries information concerning the critical dimension. However, even if this instability could be avoided, the limitation on resolution of length measurements would continue to represent a severe limitation on monitoring variation in CD; effectively preventing such monitoring at dimensions necessary for production of current and foreseeable integrated circuit designs.
The present invention provides a technique for measurement of critical dimensions of a lithographic exposure which is of increased sensitivity and accuracy without increase of process complexity or economic cost compared to known measurement techniques and characterizes exposure quality in a manner applicable to arbitrarily small critical dimensions. The invention further provides a simple, fast, accurate and repeatable technique for measurement of critical dimensions of a lithographically exposed image such as may be used in semiconductor integrated circuit manufacture and for other purposes.
These and other meritorious effects are achieved by forming a test mark, preferably by making overlapping exposures of features of known dimensions, imaging a portion of the test mark to determine an area of the test mark, and computing a dimension of the test mark from the area signal. Only a single test mark is required for each measurement and the test mark can be of very simple form that can be placed at any location on the wafer and even within an integrated circuit design pattern with little, if any, interference with the desired integrated circuit design. Measurement can be made with broadband light and does not require any special illumination, or scanning or specially adapted optical devices.